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nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 ds90lv049h high temperature 3v lvds dual line driver and receiver pair check for samples: ds90lv049h 1 features description the ds90lv049h is a dual cmos flow-through 2 ? high temperature +125 c operating range differential line driver-receiver pair designed for ? up to 400 mbps switching rates applications requiring ultra low power dissipation, ? flow-through pinout simplifies pcb layout exceptional noise immunity, and high data throughput. the device is designed to support data ? 50 ps typical driver channel-to-channel skew rates in excess of 400 mbps utilizing low voltage ? 50 ps typical receiver channel-to-channel differential signaling (lvds) technology. skew the ds90lv049h drivers accept lvttl/lvcmos ? 3.3 v single power supply design signals and translate them to lvds signals. the ? tri-state output control receivers accept lvds signals and translate them to ? internal fail-safe biasing of receiver inputs 3 v cmos signals. the lvds input buffers have internal failsafe biasing that places the outputs to a ? low power dissipation (70 mw at 3.3 v static) known h (high) state for floating receiver inputs. in ? high impedance on lvds outputs on power addition, the ds90lv049h supports a tri-state down function for a low idle power state when the device is ? conforms to tia/eia-644-a lvds standard not in use. ? available in low profile 16 pin tssop the en and en inputs are anded together and package control the tri-state outputs. the enables are common to all four gates. connection diagram dual-in-line order number ds90lv049hmt order number ds90lv049hmtx (tape and reel) pw0016a package 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. en gnd v dd en r in1- r in1+ r in2+ r in2- d out2- d out2+ d out1+ d out1- r out1 r out2 d in2 d in1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com functional diagram table 1. truth table en en lvds out lvcmos out l or open l or open off off h l or open on on l or open h off off h h off off these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h r1 r2 d1 d2 r in1- r in1+ r in2+ r in2- d out2- d out2+ d out1+ d out1- r out1 r out2 d in2 d in1 and en en
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 absolute maximum ratings (1) (2) supply voltage (v dd ) ? 0.3 v to +4 v lvcmos input voltage (d in ) ? 0.3 v to (v dd + 0.3 v) lvds input voltage (r in+ , r in- ) ? 0.3 v to +3.9 v enable input voltage (en, en) ? 0.3 v to (v dd + 0.3 v) lvcmos output voltage (r out ) ? 0.3 v to (v dd + 0.3 v) lvds output voltage (d out+ , d out- ) ? 0.3 v to +3.9 v lvcmos output short circuit current (r out ) 100 ma lvds output short circuit current (d out+ , d out ? ) 24 ma lvds output short circuit current duration (d out+ , d out ? ) continuous storage temperature range ? 65 c to +150 c lead temperature range soldering (4 sec.) +260 c maximum junction temperature +150 c maximum package power dissipation @ +25 c pw0016a package 866 mw derate pw0016a package 6.9 mw/ c above +25 c esd rating (hbm, 1.5 k , 100 pf) 7 kv (mm, 0 , 200 pf) 250 v (1) ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be specified. they are not meant to imply that the devices should be operated at these limits. electrical characteristics specifies conditions of device operation. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. recommended operating conditions min typ max units supply voltage (v dd ) +3.0 +3.3 +3.6 v operating free air temperature (t a ) ? 40 +25 +125 c electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) (3) symbol parameter conditions pin min typ max units lvcmos input dc specifications (driver inputs, enable pins) v ih input high voltage 2.0 v dd v v il input low voltage gnd 0.8 v d in i ih input high current v in = v dd en ? 10 1 +10 a en i il input low current v in = gnd ? 10 ? 0.1 +10 a v cl input clamp voltage i cl = ? 18 ma ? 1.5 ? 0.6 v lvds output dc specifications (driver outputs) (1) current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground except: v th , v tl , v od and v od . (2) all typical values are given for: v dd = +3.3 v, t a = +25 c. (3) the ds90lv049h ' s drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. the typical range of the resistor values is 90 ? to 110 ? . copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: ds90lv049h
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com electrical characteristics (continued) over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) (3) symbol parameter conditions pin min typ max units | v od | differential output voltage 250 350 450 mv v od change in magnitude of v od for 1 35 |mv| complementary output states r l = 100 ( figure 1 ) v os offset voltage 1.125 1.23 1.375 v v os change in magnitude of v os for 1 25 |mv| complementary output states i os output short circuit current (4) enabled, ? 5.8 ? 9.0 ma d out ? d in = v dd , d out+ = 0 v or d out+ d in = gnd, d out ? = 0 v i osd differential output short circuit ? 5.8 ? 9.0 ma enabled, v od = 0 v current (4) i off power-off leakage v out = 0 v or 3.6 v ? 20 1 +20 a v dd = 0 v or open i oz output tri-state current en = 0 v and en = v dd ? 10 1 +10 a v out = 0 v or v dd lvds input dc specifications (receiver inputs) v th differential input high threshold ? 15 35 mv v cm = 1.2 v, 0.05 v, 2.35 v v tl differential input low threshold -100 ? 15 mv v cmr common-mode voltage range v id = 100 mv, v dd =3.3 v 0.05 3 v r in+ v dd =3.6 v r in- ? 12 4 +12 a v in =0 v or 2.8 v i in input current v dd =0 v ? 10 1 +10 a v in =0 v or 2.8 v or 3.6 v lvcmos output dc specifications (receiver outputs) v oh output high voltage i oh = -0.4 ma, v id = 200 mv 2.7 3.3 v v ol output low voltage i ol = 2 ma, v id = 200 mv r out 0.05 0.25 v i oz output tri-state current disabled, v out =0 v or v dd -10 1 +10 a general dc specifications i dd power supply current (5) en = 3.3 v 21 35 ma v dd i ddz tri-state supply current en = 0 v 15 25 ma (4) output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. (5) both driver and receiver inputs are static. all lvds outputs have 100 ? load. all lvcmos outputs are floating. none of the outputs have any lumped capacitive load. 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 switching characteristics v dd = +3.3v 10%, t a = ? 40 c to +125 c (1) (2) symbol parameter conditions min typ max units lvds outputs (driver outputs) t phld differential propagation delay high to low 0.7 2 ns t plhd differential propagation delay low to high 0.7 2 ns t skd1 differential pulse skew |t phld ? t plhd | (3) (4) 0 0.05 0.4 ns r l = 100 t skd2 differential channel-to-channel skew (3) (5) 0 0.05 0.5 ns ( figure 2 and figure 3 ) t skd3 differential part-to-part skew (3) (6) 0 1.0 ns t tlh rise time (3) 0.2 0.4 1 ns t thl fall time (3) 0.2 0.4 1 ns t phz disable time high to z 1.5 3 ns t plz disable time low to z 1.5 3 ns r l = 100 ( figure 4 and figure 5 ) t pzh enable time z to high 1 3 6 ns t pzl enable time z to low 1 3 6 ns f max maximum operating frequency (7) 200 250 mhz lvcmos outputs (receiver outputs) t phl propagation delay high to low 0.5 2 3.5 ns t plh propagation delay low to high 0.5 2 3.5 ns t sk1 pulse skew |t phl ? t plh | (8) 0 0.05 0.4 ns t sk2 channel-to-channel skew (9) ( figure 6 and figure 7 ) 0 0.05 0.5 ns t sk3 part-to-part skew (10) 0 1.0 ns t tlh rise time (3) 0.3 0.9 1.4 ns t thl fall time (3) 0.3 0.75 1.4 ns t phz disable time high to z 3 5.6 8 ns t plz disable time low to z 3 5.4 8 ns ( figure 8 and figure 9 ) t pzh enable time z to high 2.5 4.6 7 ns t pzl enable time z to low 2.5 4.6 7 ns f max maximum operating frequency (11) 200 250 mhz (1) all typical values are given for: v dd = +3.3 v, t a = +25 c. (2) generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50 , t r 1 ns, and t f 1 ns. (3) these parameters are specified by design. the limits are based on statistical analysis of the device performance over pvt (process, voltage, temperature) ranges. (4) t skd1 or differential pulse skew is defined as |t phld ? t plhd |. it is the magnitude difference in the differential propagation delays between the positive going edge and the negative going edge of the same driver channel. (5) t skd2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels on the same device. (6) t skd3 or differential part-to-part skew is defined as |t plhd max ? t plhd min | or |t phld max ? t phld min |. it is the difference between the minimum and maximum specified differential propagation delays. this specification applies to devices at the same v dd and within 5 c of each other within the operating temperature range. (7) f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, 0 v to 3 v. output criteria: duty cycle = 45%/55%, v od > 250 mv, all channels switching. (8) t sk1 or pulse skew is defined as |t phl ? t plh |. it is the magnitude difference in the propagation delays between the positive going edge and the negative going edge of the same receiver channel. (9) t sk2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device. (10) t sk3 or part-to-part skew is defined as |t plh max ? t plh min | or |t phl max ? t phl min |. it is the difference between the minimum and maximum specified propagation delays. this specification applies to devices at the same v dd and within 5 c of each other within the operating temperature range. (11) f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, v id = 200 mv, v cm = 1.2 v . output criteria: duty cycle = 45%/55%, v oh > 2.7 v, v ol < 0.25 v, all channels switching. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: ds90lv049h
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com parameter measurement information figure 1. driver v od and v os test circuit figure 2. driver propagation delay and transition time test circuit figure 3. driver propagation delay and transition time waveforms 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h transmission line transmission line dc block dc block signal generator transmission line d 50 : 50 : 50 : oscilloscope z 0 = 50 : c = 15 pf distributed z 0 = 50 : c = 15 pf distributed d in d out+ d out- power supply v dd en 100 : smu smu smu d d in d out+ d out- power supply v dd en 100 :
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 parameter measurement information (continued) figure 4. driver tri-state delay test circuit figure 5. driver tri-state delay waveform figure 6. receiver propagation delay and transition time test circuit copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: ds90lv049h transmission line transmission line signal generator transmission line d 50 : 50 : 50 : oscilloscope z 0 = 50 : c = 15 pf distributed z 0 = 50 : c = 15 pf distributed en d out+ d out- 3.3 v d in v dd 100 : 2.4 v 1 k : 1 k : 950 : 950 : power supplies 2.4 v transmission line power supply r 950 : 50 : oscilloscope z 0 = 50 : c = 15 pf distributed en r out power supply transmission line 100 : z 0 = 50 : c = 15 pf distributed r in+ signal generator transmission line r in- v dd
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com parameter measurement information (continued) figure 7. receiver propagation delay and transition time waveforms figure 8. receiver tri-state delay test circuit 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h transmission line signal generator transmission line r 50 : 950 : 50 : oscilloscope z 0 = 50 : c = 15 pf distributed z 0 = 50 : c = 15 pf distributed en r out 1.4 v 100 : r in+ 1.0 v r in- v dd power supplies 2.5 v 1 k :
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 parameter measurement information (continued) figure 9. receiver tri-state delay waveforms typical application figure 10. point-to-point application copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: ds90lv049h en en 1.5 v 3 v 0 v t plz t phz 0.5 v 0.5 v 1.5 v 1.5 v 1.5 v t pzl t pzh v dd / 2 v ol v dd / 2 v oh 50% 50% out out 0 v 3 v
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com application information general application guidelines and hints for lvds drivers and receivers may be found in the following application notes: lvds owner's manual (lit #550062-003), an-808 ( snla028 ), an-977 ( snla166 ), an-971 ( snla165 ), an-916 ( snla219 ), an-805 ( snoa233 ), an-903 ( snla034 ). lvds drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in figure 10 . this configuration provides a clean signaling environment for the fast edge rates of the drivers. the receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply pcb traces. typically, the characteristic differential impedance of the media is in the range of 100 . a termination resistor of 100 (selected to match the media), and is located as close to the receiver input pins as possible. the termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. the tri-state function allows the device outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. the ds90lv049h has a flow-through pinout that allows for easy pcb layout. the lvds signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. noise isolation is achieved with the lvds signals on one side of the device and the ttl signals on the other side. power decoupling recommendations bypass capacitors must be used on power pins. use high frequency ceramic (surface mount is recommended) 0.1 f and 0.001 f capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. additional scattered capacitors over the printed circuit board will improve decoupling. multiple vias should be used to connect the decoupling capacitors to the power planes. a 10 f (35 v) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. pc board considerations use at least 4 pcb layers (top to bottom); lvds signals, ground, power, ttl signals. isolate ttl signals from lvds signals, otherwise the ttl may couple onto the lvds lines. it is best to put ttl and lvds signals on different layers which are isolated by a power/ground plane(s). keep drivers and receivers as close to the (lvds port side) connectors as possible. differential traces use controlled impedance traces which match the differential impedance of your transmission medium (that is, cable) and termination resistor. run the differential pair trace lines as close together as possible as soon as they leave the ic (stubs should be < 10 mm long). this will help eliminate reflections and ensure noise is coupled as common-mode. in fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic field cancellation is much better with the closer traces. in addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. match electrical lengths between traces to reduce skew. skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and emi will result. (note the velocity of propagation, v = c/er where c (the speed of light) = 0.2997 mm/ps or 0.0118 in/ps). do not rely solely on the autoroute function for differential traces. carefully review dimensions to match differential impedance and provide isolation for the differential lines. minimize the number or vias and other discontinuities on the line. avoid 90 turns (these cause impedance discontinuities). use arcs or 45 bevels. within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. on the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. minor violations at connection points are allowable. 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 termination use a termination resistor which best matches the differential impedance or your transmission line. the resistor should be between 90 ? and 130 ? . remember that the current mode outputs need the termination resistor to generate the differential voltage. lvds will not work without resistor termination. typically, connecting a single resistor across the pair at the receiver end will suffice. surface mount 1% to 2% resistors are best. pcb stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. the distance between the termination resistor and the receiver should be < 10 mm (12 mm max). probing lvds transmission lines always use high impedance ( > 100 k ? ), low capacitance ( < 2 pf) scope probes with a wide bandwidth (1 ghz) scope. improper probing will give deceiving results. cables and connectors, general comments when choosing cable and connectors for lvds it is important to remember: use controlled impedance media. the cables and connectors you use should have a matched differential impedance of about 100 ? . they should not introduce major impedance discontinuities. balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. balanced cables tend to generate less emi due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. fail-safe feature an lvds receiver is a high gain, high speed device that amplifies a small differential signal (20 mv) to cmos logic levels. due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. the receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating receiver inputs. the ds90lv049h has two receivers, and if an application requires a single receiver, the unused receiver inputs should be left open. do not tie unused receiver inputs to ground or any other voltages. the input is biased by internal high value pull up and pull down current sources to set the output to a high state. this internal circuitry will ensure a high, stable output state for open inputs. external lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. the pull up and pull down resistors should be in the 5 k ? to 15 k ? range to minimize loading and waveform distortion to the driver. the common-mode bias point should be set to approximately 1.2 v (less than 1.75 v) to be compatible with the internal circuitry. for more information on failsafe biasing of lvds interfaces please refer to an-1194. pin descriptions pin no. name description 10, 11 d in driver input pins, lvcmos levels. there is a pull-down current source present. 6, 7 d out+ non-inverting driver output pins, lvds levels. 5, 8 d out ? inverting driver output pins, lvds levels. 2, 3 r in+ non-inverting receiver input pins, lvds levels. there is a pull-up current source present. 1, 4 r in- inverting receiver input pins, lvds levels. there is a pull-down current source present. 14, 15 r out receiver output pins, lvcmos levels. 9, 16 en, en enable and disable pins. there are pull-down current sources present at both pins. 12 v dd power supply pin. 13 gnd ground pin. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: ds90lv049h
nrnd ds90lv049h snls200a ? september 2005 ? revised april 2013 www.ti.com typical performance curves differential output voltage power supply current vs load resistor vs frequency 12 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: ds90lv049h 0.1 1 10 100 1000 frequency - f [mhz] 0 15 30 45 60 75 90 power supply current - i dd [ma] single receiver switching all switching single driver switching v dd = 3.3 v t a = 25 o c r l = 100 : c l = 15 pf v id = 0.4 v v in = 3.3 v 40 60 80 100 120 140 160 resistor load - r l [ : ] 0.25 0.30 0.35 0.40 0.45 differential output voltage - v od [v] v dd = 3.3 v t a = 25 o c
nrnd ds90lv049h www.ti.com snls200a ? september 2005 ? revised april 2013 revision history changes from original (april 2013) to revision a page ? changed layout of national data sheet to ti format .......................................................................................................... 12 copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: ds90lv049h
package option addendum www.ti.com 30-oct-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ds90lv049hmt/nopb nrnd tssop pw 16 92 green (rohs & no sb/br) cu sn level-1-260c-unlim 90lv049 hmt ds90lv049hmtx/nopb nrnd tssop pw 16 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim 90lv049 hmt (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 30-oct-2013 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ds90lv049hmtx/nopb tssop pw 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 6-nov-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ds90lv049hmtx/nopb tssop pw 16 2500 367.0 367.0 35.0 package materials information www.ti.com 6-nov-2015 pack materials-page 2

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